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CXD3615R
Timing Generator for Frame Readout CCD Image Sensor
Description The CXD3615R is a timing generator IC which generates the timing pulses for performing frame readout using the ICX432/434 CCD image sensor. Features * Base oscillation frequency 48.6/36.0MHz * Electronic shutter function * Supports draft, AF mode * H/V driver for CCD Applications Digital still cameras Structure Silicon gate CMOS IC Applicable CCD Image Sensors * ICX432 (Type 1/2.7, 3240K pixels) * ICX434 (Type 1/3.2, 2020K pixels) 48 pin LQFP (Plastic)
Absolute Maximum Ratings * Supply voltage VDD VSS - 0.3 to +7.0 V VL -10.0 to VSS V VH VL - 0.3 to +26.0 V * Input voltage VI VSS - 0.3 to VDD + 0.3 V VSS - 0.3 to VDD + 0.3 V * Output voltage VO1 VO2 VL - 0.3 to VSS + 0.3 V VO3 VL - 0.3 to VH + 0.3 V * Operating temperature Topr -20 to +75 C * Storage temperature Tstg -55 to +150 C Recommended Operating Conditions * Supply voltage VDDa, VDDb, VDDc 3.0 to 3.6 VM 0.0 VH 14.5 to 15.5 VL -7.0 to -8.0 * Operating temperature Topr -20 to +75
Pin Configuration
MCKO OSCO OSCI VDD5 VSS5 CKO SEN SCK CKI SSI HR VR
36 VM V4 V2 V5A VH V5B V1 V3A VL V3B V6 SUB 37 38 39 40 41 42 43 44 45 46 47 48 1
VSS1
35
34
33
32
31
30
29
28
27
26
25 24 VSS4 23 ADCLK 22 OBCLP 21 TEST2 20 CLPDM 19 PBLK 18 TEST1 17 XSHD 16 XSHP 15 VDD4 14 VDD3 13 H2
V V V V C
Groups of pins enclosed in the figure indicate sections for which power supply separation is possible.
2
RST
3
SNCSL
4
ID/EXP
5
WEN/FLD
6
SSGSL
7
VDD1
8
VDD2
9
RG
10
VSS2
11
VSS3
12
H1
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
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E02216-PS
CXD3615R
Block Diagram
ADCLK
VSS3
H1
H2
11 12 13 14 OSCI OSCO 28 27
Sel
8
9
10
16 17 23
CKG 19 PBLK
CKI
26
Sel
XSHD
XSHP
VDD3
VDD2
VSS2
RG
20 CLPDM SHT H/VTM 22 OBCLP 4 5 ID/EXP WEN/FLD
1/2 MCKO 30 CKO 25
1/2
SNCSL
3
Selector
Latch
39 V2 38 V4 47 V6 43 V1 44 V3A
SSI 31 SCK 32 SEN 33
Selector
Register
V Driver
46 V3B 40 V5A 42 V5B 48 SUB 37 VM 41 VH 45 VL
SSGSL
6 SSG
RST
2
TEST1 18 TEST2 21
1
VSS1
24 36
VSS4 VSS5
7
VDD1
15 29
VDD4 VDD5
35 34
HR VR
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CXD3615R
Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Symbol VSS1 RST SNCSL ID/EXP WEN/FLD SSGSL VDD1 VDD2 RG VSS2 VSS3 H1 H2 VDD3 VDD4 XSHP XSHD TEST1 PBLK CLPDM TEST2 OBCLP ADCLK VSS4 CKO CKI OSCO OSCI VDD5 MCKO I/O -- I I O O I -- -- O -- -- O O -- -- O O I O O -- O O -- O I O I -- O GND Internal system reset input. High: Normal operation, Low: Reset control Normally apply reset during power-on. Schmitt trigger input Control input used to switch sync system. High: CKI sync, Low: MCKO sync With pull-down resistor Description
Vertical direction line identification pulse output/exposure time identification pulse output. Switching possible using the serial interface data. (Default: ID) Memory write timing pulse output/field discrimination pulse output. Switching possible using the serial interface data. (Default: WEN) Internal SSG enable. High: Internal SSG valid, Low: External sync valid With pull-down resistor
3.3V power supply. (Power supply for common logic block) 3.3V power supply. (Power supply for RG) CCD reset gate pulse output. GND GND CCD horizontal register clock output. CCD horizontal register clock output. 3.3V power supply. (Power supply for H1/H2) 3.3V power supply. (Power supply for CDS) CCD precharge level sample-and-hold pulse output. CCD data level sample-and-hold pulse output. IC test pin 1; normally fixed to GND. CCD dummy signal clamp pulse output. IC test pin 2; normally fixed to GND. With pull-down resistor CCD optical black signal clamp pulse output. The horizontal/vertical OB pattern can be changed using the serial interface data. Clock output for analog/digital conversion IC. Logical phase adjustment possible using the serial interface data. GND Inverter output. Inverter input. Inverter output for oscillation. When not used, leave open or connect a capacitor. Inverter input for oscillation. When not used, fix to low. 3.3V power supply. (Power supply for common logic block) System clock output for signal processing IC. With pull-down resistor Pulse output for horizontal and vertical blanking period pulse cleaning
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CXD3615R
Pin No. 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
Symbol SSI SCK SEN VR HR VSS5 VM V4 V2 V5A VH V5B V1 V3A VL V3B V6 SUB
I/O I I I I/O I/O -- -- O O O -- O O O -- O O O
Description Serial interface data input for internal mode settings. Schmitt trigger input Serial interface clock input for internal mode settings. Schmitt trigger input Serial interface strobe input for internal mode settings. Schmitt trigger input Vertical sync signal input/output. Horizontal sync signal input/output. GND GND (GND for vertical driver) CCD vertical register clock output/V2 for ICX434. CCD vertical register clock output/open for ICX434. CCD vertical register clock output/V3A for ICX434. 15.0V power supply. (Power supply for vertical driver) CCD vertical register clock output/V3B for ICX434. CCD vertical register clock output/open for ICX434. CCD vertical register clock output//V1A for ICX434. -7.5V power supply. (Power supply for vertical driver) CCD vertical register clock output/V1B for ICX434. CCD vertical register clock output//V4 for ICX434. CCD electronic shutter pulse output.
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CXD3615R
Electrical Characteristics DC Characteristics Item Pins Symbol VDDa VDDb VDDc Vt+ Vt- 0.7VDDc 0.3VDDc 0.8VDDc 0.2VDDc Feed current where IOH = -1.2mA VDDc - 0.8 Pull-in current where IOL = 2.4mA Feed current where IOH = -14.0mA VDDa - 0.8 Pull-in current where IOL = 9.6mA Feed current where IOH = -3.3mA VDDb - 0.8 Pull-in current where IOL = 2.4mA Feed current where IOH = -3.3mA VDDc - 0.8 Pull-in current where IOL = 2.4mA Feed current where IOH = -6.9mA VDDc - 0.8 Pull-in current where IOL = 4.8mA Feed current where IOH = -3.3mA VDDc - 0.8 Pull-in current where IOL = 2.4mA Feed current where IOH = -2.4mA VDDc - 0.8 Pull-in current where IOL = 4.8mA V1, V2, V3A/B, V4, V5A/B, V6 = -8.25V V1, V2, V3A/B, V4, V5A/B, V6 = -0.25V V1, V3A/B, V5A/B = 0.25V V1, V3A/B, V5A/B = 14.75V SUB = -8.25V SUB = 14.75V 5.4 -4.0 5.0 -7.2 10.0 -5.0 0.4 0.4 0.4 0.4 0.4 0.4 0.4 (Within the recommended operating conditions) Conditions Min. 3.0 3.0 3.0 0.8VDDc 0.2VDDc Typ. 3.3 3.3 3.3 Max. 3.6 3.6 3.6 Unit V V V V V V V V V V V V V V V V V V V V V V V mA mA mA mA mA mA
Supply voltage 1 VDD3 Supply voltage 2 VDD2 Supply voltage 3 VDD1, VDD4, VDD5
RST, SSI, Input voltage 11 SCK, SEN
TEST1, TEST2, VIH1 Input voltage 22 SNCSL, SSGSL VIL1 VIH2 Input/output voltage VR, HR VIL2 VOH1 VOL1 Output voltage 1 H1, H2 Output voltage 2 RG VOH2 VOL2 VOH3 VOL3
XSHP XSHD, VOH4 , PBLK, OBCLP , Output voltage 3 CLPDM, VOL4 ADCLK Output voltage 4 CKO Output voltage 5 MCKO Output voltage 6 ID/EXP , WEN/FLD VOH5 VOL5 VOH6 VOL6 VOH7 VOL7 IOL V1, V3A, V3B, Output current 1 V5A, V5B, V2, V4, V6 IOM1 IOM2 IOH Output current 2 SUB IOSL IOSH
1 These input pins are Schmitt trigger inputs. 2 This input pin is with pull-down register in the IC.
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CXD3615R
Inverter I/O Characteristics for Oscillation Item Logical Vth Input voltage Output voltage Feedback resistor Oscillation frequency Pins OSCI OSCI OSCO OSCI, OSCO OSCI, OSCO Symbol LVth VIH VIL VOH VOL RFB f
(Within the recommended operating conditions) Conditions Min. 0.7VDDc 0.3VDDc Typ. VDDc/2 Max. Unit V V V V 0.4 500k 20 2M 5M 50 V MHz
Feed current where IOH = -3.6mA VDDc - 0.8 Pull-in current where IOL = 2.4mA VIN = VDDc or VSS
Inverter Input Characteristics for Base Oscillation Clock Duty Adjustment (Within the recommended operating conditions) Item Logical Vth Input voltage Input amplitude CKI Pins Symbol LVth VIH VIL VIN fmax 50MHz sine wave 0.3 0.7VDDc 0.3VDDc Conditions Min. Typ. VDDc/2 Max. Unit V V V Vp-p
Note) Input voltage is the input voltage characteristics for direct input from an external source. Input amplitude is the input amplitude characteristics in the case of input through a capacitor. Switching Characteristics Item Rise time Symbol TTLM TTMH TTLH TTML Fall time TTHM TTHL VCLH Output noise voltage VCLL VCMH VCML Conditions VL to VM VM to VH VL to VH VM to VL VH to VM VH to VL (VH = 15.0V, VM = GND, VL = -7.5V) Min. 200 200 30 200 200 30 Typ. 350 350 60 350 350 60 Max. 500 500 90 500 500 90 1.0 1.0 1.0 1.0 Unit ns ns ns ns ns ns V V V V
Notes) 1) The MOS structure of this IC has a low tolerance for static electricity, so full care should be given for measures to prevent electrostatic discharge. 2) For noise and latch-up countermeasures, be sure to connect a by-pass capacitor (0.1F or more) between each power supply pin (VH, VL) and GND. 3) To protect the CCD image sensor, clamp the SUB pin output at VH before input to the CCD image sensor. -6-
CXD3615R
Switching Waveforms
TTMH 90% TTHM VH 90%
V1 (V3A, V3B, V5A, V5B)
TTLM
10% 90%
10% 90%
TTML
VM
10%
10%
VL
TTLM 90% V2 (V4, V6) 10% 90%
TTML
VM
10%
VL
TTLH 90% 90%
TTHL
VH
SUB
10%
10% VL
Waveform Noise
VM VCMH VCML
VCLH VCLL VL
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CXD3615R
Measurement Circuit
Serial interface data
VR HR +3.3V -7.5V +15.0V 36 35 34 33 32 31 30 29 28 27 26 25 37 R1 C2 R1 C1 C2 C1 C2 C2 C2 C1 C2 C2 C1 C2 R1 C2 R2 C3 C1 C2 C2 C1 C2 C2 R1 38 39 40 41 42 43 44 R1 45 46 47 48 1 2 3 4 5 6 7 8 9 10 11 12 CXD3615R 24 23 22 21 20 19 18 17 16 15 14 13 C5 C6 C6 C6 C6 C6 C6 C6 C6
CKI
C2 C2
R1
C4
C5
C1: 3300pF R1: 30
C2: 560pF R2: 10
C3: 820pF
C4: 8pF
C5: 140pF
C6: 10pF
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CXD3615R
AC Characteristics AC characteristics between the serial interface clocks
0.8VDDc SSI SCK SEN SEN ts2 0.2VDDc 0.8VDDc 0.2VDDc ts1 0.2VDDc ts3 0.8VDDc
th1
(Within the recommended operating conditions) Symbol Definition SSI setup time, activated by the rising edge of SCK SSI hold time, activated by the rising edge of SCK SCK setup time, activated by the rising edge of SEN SEN setup time, activated by the rising edge of SCK Min. 20 20 20 20 Typ. Max. Unit ns ns ns ns
ts1 th1 ts2 ts3
Serial interface clock internal loading characteristics (1)
Example: During frame mode VR HR V1 Enlarged view HR 0.2VDDc
V1 ts1 SEN 0.8VDDc 0.2VDDc th1
Be sure to maintain a constantly high SEN logic level near the falling edge of the HR in the horizontal period during which V1, V3A/B and V5A/B values take the ternary value and during that horizontal period. (Within the recommended operating conditions) Symbol Definition SEN setup time, activated by the falling edge of HR SEN hold time, activated by the falling edge of HR Min. 0 123 Typ. Max. Unit ns s
ts1 th1
Restriction for the ICX432 operating frequency of 24.3MHz in draft mode -9-
CXD3615R
Serial interface clock internal loading characteristics (2)
Example: During frame mode VR HR Enlarged view
VR HR
0.2VDDc
ts1 SEN 0.8VDDc
th1 0.2VDDc
Be sure to maintain a constantly high SEN logic level near the falling edge of VR. (Within the recommended operating conditions) Symbol Definition SEN setup time, activated by the falling edge of VR SEN hold time, activated by the falling edge of VR Min. 0 200 Typ. Max. Unit ns ns
ts1 th1
Restriction for the ICX432 operating frequency of 24.3MHz in draft mode
Serial interface clock output variation characteristics Normally, the serial interface data is loaded to the CXD3615R at the timing shown in "Serial interface clock internal loading characteristics (1)" above. However, one exception to this is when the data such as STB is loaded to the CXD3615R and controlled at the rising edge of SEN. See "Description of Operation".
SEN
0.8VDDc
Output signal tpdPULSE
(Within the recommended operating conditions) Symbol Definition Min. 5 Typ. Max. 100 Unit ns
tpdPULSE Output signal delay, activated by the rising edge of SEN
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CXD3615R
RST loading characteristics
RST
0.2VDDc tw1
0.2VDDc
(Within the recommended operating conditions) Symbol Definition RST pulse width Min. 35 Typ. Max. Unit ns
tw1
VR and HR phase characteristics
VR 0.2VDDc ts1 HR th1 0.2VDDc 0.2VDDc
(Within the recommended operating conditions) Symbol Definition VR setup time, activated by the falling edge of HR VR hold time, activated by the falling edge of HR Min. 0 0 Typ. Max. Unit ns ns
ts1 th1
HR loading characteristics
HR 0.2VDDc ts1 MCKO th1 0.8VDDc 0.2VDDc
MCKO load capacitance = 10pF (Within the recommended operating conditions) Symbol Definition HR setup time, activated by the rising edge of MCKO HR hold time, activated by the rising edge of MCKO Min. 13 0 Typ. Max. Unit ns ns
ts1 th1
Output variation characteristics
MCKO WEN/FLD, ID/EXP tpd1 0.8VDDc
WEN/FLD and ID/EXP load capacitance = 10pF (Within the recommended operating conditions) Symbol Definition Time until the above outputs change after the rise of MCKO - 11 - Min. 20 Typ. Max. 60 Unit ns
tpd1
CXD3615R
Description of Operation Pulses output from the CXD3615R are controlled mainly by the RST pin and by the serial interface data. The Pin Status Table is shown below, and the details of serial interface control are described on the following pages. Pin Status Table Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Symbol VSS1 RST SNCSL ID/EXP SSGSL VDD1 VDD2 RG VSS2 VSS3 H1 H2 VDD3 VDD4 XSHP XSHD TEST1 PBLK CLPDM TEST2 OBCLP ADCLK VSS4 ACT ACT L L ACT ACT L L ACT ACT L L ACT ACT L L ACT L ACT ACT ACT ACT ACT ACT L L ACT CAM SLP SST -- ACT ACT L L ACT -- -- L -- -- L L -- -- L L -- L L -- L L -- L L H ACT L L H H L L ACT ACT L L ACT ACT L ACT ACT ACT L L ACT L ACT L L ACT STB RST Pin No. 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Symbol CKO CKI OSCO OSCI VDD5 MCKO SSI SCK SEN VR1 HR1 VSS5 VM V4 V2 V5A VH V5B V1 V3A VL V3B V6 SUB ACT ACT ACT VH VM VH ACT ACT ACT VH VH VH ACT ACT ACT VM VM VH ACT ACT ACT ACT ACT ACT ACT ACT ACT ACT L L CAM ACT ACT ACT ACT SLP ACT ACT ACT ACT SST L ACT ACT ACT -- L ACT ACT ACT L L -- -- VM VM VM -- VM VM VM -- VM VM VL VH VM VH VM VL VL VH VH VH VL VM VM VM VM VH VM VM VL L ACT ACT ACT L L ACT DIS DIS DIS H H STB L ACT ACT ACT RST ACT ACT ACT ACT
WEN/FLD ACT
1 It is for output. For input, all items are "ACT". Note) ACT means that the circuit is operating, and DIS means that loading is stopped. L indicates a low output level, and H a high output level in the controlled status. Also, VH, VM and VL indicate the voltage levels applied to VH (Pin 41), VM (Pin 37) and VL (Pin 45), respectively, in the controlled status.
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CXD3615R
Serial Interface Control The CXD3615R basically loads and reflects the serial interface data sent in the following format in the readout portion at the falling edge of HR. Here, readout portion specifies the horizontal period during which V1, V3A/B and V5A/B, etc. take the ternary value. Note that some items reflect the serial interface data at the falling edge of VR or the rising edge of SEN.
SSI SCK SEN
00
01
02
03
04
05
06
41
42
43
44
45
46
47
These are two categories of serial interface data: the CXD3615R drive control data (hereafter "control data") and electronic shutter data (hereafter "shutter data"). The details of each data are described below.
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CXD3615R
Control Data Data D00 to D07 D09 to D11 Symbol CHIP Chip enable Category switching -- Drive mode switching -- Internal SSG function switching1 CCD switching1 -- Electronic shutter mode switching2 HTSG control switching2 -- WEN/FLD output switching Wide OBCLP generation switching ID/EXP output switching OBCLP waveform pattern switching ADCLK logic phase adjustment Standby control -- Function Data = 0 Data = 1 RST All 0 0 All 0 0 0 0 0 0 0 0 All 0 0 0 0 All 0 All 0 All 0 All 0
10000001 Enabled Other values Disabled See the category section. -- --
D08 CTG --
D12, MODE D13 D14, D15 D16 D17 D18, D19 D20 D21 D22 to D30 D31 D32 D33 -- NTPL CCD -- SMD HTSG -- FLD FGOB EXP
See the drive mode section. -- NTSC ICX432 -- OFF OFF -- WEN OFF ID -- PAL ICX434 -- ON ON -- FLD ON EXP
D34, PTOB D35 D36, LDAD D37 D38, STB D39 D40 to D47 --
See the OBCLP waveform pattern section. See the ADCLK logic phase section. See the standby section. -- --
1 See the drive mode section. 2 See the electronic shutter section.
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CXD3615R
Shutter Data Data D00 to D07 D09 Symbol CHIP Chip enable Category switching -- Electronic shutter vertical period specification Electronic shutter horizontal period specification High-speed shutter position specification -- Function Data = 0 Data = 1 RST All 0 0 0 All 0 All 0 All 0 All 0
10000001 Enabled Other values Disabled See the category section. -- --
D08 CTG -- D10 to SVR D19 D20 to D31 D32 to D41 D42 to D47 SHR
See the electronic shutter section.
See the electronic shutter section.
SPL
See the electronic shutter section.
--
--
--
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CXD3615R
Detailed Description of Each Data Shared data: D08 CTG [Category] Of the data provided to the CXD3615R by the serial interface, the CXD3615R loads D09 and subsequent data to each data register as shown in the table below according to D08 . D08 0 1 Description of operation Loading to control data register Loading to shutter data register
Note that the CXD3615R can apply these categories consecutively within the same vertical period. However, care should be taken as the data is overwritten if the same category is applied. Control data: D12 and D13 MODE [Drive mode] The CXD3615R realizes various drive modes using control data D12 and D13 MODE, D16 NTPL and D17 CCD. The drive mode-related bits are loaded to the CXD3615R and reflected at the falling edge of VR. The details are described below. First, the various basic drive modes are shown below. These modes are switched using control data D12 and D13 MODE. D13 0 0 1 1 D12 0 1 0 1 Description of operation Draft mode (default) Frame mode AF mode1 Test mode
1 These are both test mode for the ICX434. Draft mode is the pulse elimination drive mode in the ICX432/434. AF mode is the pulse eliminator drive mode based on draft mode, and is a high frame rate drive mode that can be used for purposes such as auto focus (AF). Frame mode is the ICX432/434 drive mode in which the data for all lines are read. In addition to these modes, the CXD3615R has functions for switching the applicable CCD with D17 CCD, and for switching VR/HR to NTSC equivalent or PAL equivalent with D16 NTPL. Control data: D31 FLD [WEN/FLD output switching] The WEN/FLD pin (Pin 5) output can be switched to the WEN pulse or the FLD pulse. The default is "WEN". See the Timing Charts for the WEN pulse. The FLD pulse rises in the readout block in the A Field, and falls in the horizontal period immediately thereafter. That is to say, FLD is a 1H high-active pulse. The transition points are the same as for ID/WEN.
HR VCK FLD
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CXD3615R
Control data: D32 FGOB [Wide OBCLP generation] This controls wide OBCLP generation during the vertical OPB period. When this function is on, the D34 and D35 PTOB setting is invalid for the output block. See the Timing Charts for the actual operation. The default is "OFF". D32 0 1 Description of operation Wide OBCLP generation OFF Wide OBCLP generation ON
Control data D34 and D35 PTOB [OBCLP waveform pattern] This designates the OBCLP waveform pattern. The default is "Normal". See the Timing Charts for details of the decoding values. D35 0 0 1 1 D34 0 1 0 1 Waveform pattern (Normal) (Shifted rearward) (Shifted forward) (Wide) ICX432 20 to 44 14 to 38 26 to 50 14 to 50 ICX434 19 to 45 13 to 39 25 to 51 13 to 51
Control data: D36 and D37 LDAD [ADCLK logic phase] This indicates the ADCLK logic phase adjustment data. The default is "90" relative to MCKO. D37 0 0 1 1 D36 0 1 0 1 Degree of adjustment () 0 90 180 270
Control data: D38 and D39 STB [Standby] The operating mode is switched as follows. However, the standby bits are loaded to the CXD3615R and control is applied immediately at the rising edge of SEN. D39 0 0 1 1 D38 0 1 0 1 Symbol CAM SLP SST STB Operating mode Normal operating mode Sleep mode Siesta mode Standby mode
See the Pin Status Table for the pin status in each mode.
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CXD3615R
Control data/shutter data: [Electronic shutter] The CXD3615R realizes various electronic shutter functions by using control data D20 SMD and D21 HTSG and shutter data D10 to D19 SVR, D20 to D31 SHR and D32 to D41 SPL. These functions are described in detail below. First, the various modes are shown below. These modes are switched using control data D20 SMD. D20 0 1 Description of operation Electronic shutter stopped mode Electronic shutter mode
The electronic shutter data is expressed as shown in the table below using D20 to D31 SHR as an example. However, MSB (D31) is a reserved bit for the future specification, and is handled as a dummy bit on this IC. MSB X 0 0 1 1 1 0 0 0 0 1 LSB 1 SHR is expressed as 1C3h .
D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 1 C 3
[Electronic shutter stopped mode] During this mode, all shutter data items are invalid. SUB is not output in this mode, so the shutter speed is the accumulation time for one field. [Electronic shutter mode] During this mode, the shutter data items have the following meanings. Symbol SVR SHR SPL Data Shutter: D10 to D19 Shutter: D20 to D31 Shutter: D32 to D41 Description Number of vertical periods specification (000h SVR 3FFh) Number of horizontal periods specification (000h SHR 7FFh) Vertical period specification for high-speed shutter operation (000h SPL 3FFh)
Note) The bit data definition area is assured in terms of the CXD3615R functions, and does not assure the CCD characteristics. The period during which SVR and SHR are specified together is the shutter speed. An image of the exposure time calculation formula is shown below. In actual operation, the precise exposure time is calculated from the operating frequency, VR and HR periods, decoding value during the horizontal period, and other factors. (Exposure time) = SVR x (1V period) + {(number of HR per 1V) - (SHR + 1)} x (1H period) + (distance from SUB to SG during the readout period) Concretely, when specifying high-speed shutter, SVR is set to "000h". (See the figure.) During low-speed shutter, or in other words when SVR is set to "001h" or higher, the serial interface data is not loaded until this period is finished. The vertical period indicated here corresponds to one field in each drive mode. In addition, the number of horizontal periods applied to SHR can be considered as (number of SUB pulses - 1). The readout period is normally the horizontal period during which V1, V3A/B and V5A/B (for the ICX432) are ternary values, and SG indicates these ternary level readout pulses. - 18 -
CXD3615R
VR V3A SUB WEN EXP SMD SVR SHR Exposure time
SHR
SVR
1 002h 10Fh
1 000h 050h
Further, SPL can be used during this mode to specify the SUB output at the desired vertical period during the low-speed shutter period. In the case below, SUB is output based on SHR at the SPL vertical period out of (SVR + 1) vertical periods.
SPL 000 VR SHR V3A SUB WEN EXP SMD SPL SVR SHR Exposure time 1 001h 002h 10Fh 1 000h 000h 0A3h 001 SVR 002
Incidentally, SPL is counted as "000h", "001h", "002h" and so on in conformance with SVR. Using this function it is possible to achieve smooth exposure time transitions when changing from low-speed shutter to high-speed shutter or vice-versa.
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CXD3615R
[HTSG control mode] This mode controls the V1, V3A/B and V5A/B (for the ICX432) ternary level outputs (readout pulse block) using D21 HTSG. D21 0 1 Description of operation Readout pulse (SG) normal operation HTSG control mode
VR V3A
SUB WEN EXP HTSG SMD Exposure time 0 1 1 0 0 1
[EXP pulse] The ID/EXP pin (Pin 4) output can be switched between the ID pulse or the EXP pulse using D33 EXP. The default is the "ID" pulse. See the Timing Charts for the ID pulse. The EXP pulse indicates the exposure time when it is high. In principle, the transition points are the last SUB pulse falling edge and the readout pulse falling edge, that is to say from the time the charge is completely discharged until transfer ends. However, when the readout pulse timing differs within the same readout block such as in draft mode, the average value is used. Then, when there is no SUB pulse in the next field, the readout pulse falling edge is defined as the start position. However, in this case the transition points overlap and disappear, so a tentative start position is defined. This is shown below. SG [ICX432] Frame mode Draft/AF mode Frame mode Draft mode 1460 1682 A: 1071 B: 1175 1123 Tentative start position 1480 1784 1091 1195 1175
[ICX434]
See the EXP pulse indicated in the explanatory diagrams under [Electronic shutter] for an image of operation.
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Chart-A1
Frame mode
A Field B Field C Field
Vertical Direction Timing Chart
* ICX432
MODE
Applicable CCD image sensor
VR
43 564 588 1 43 564 588 1 43
565
588 1
HR
SUB A
High-speed sweep block High-speed sweep block
D
High-speed sweep block
B
C
V1
V2
V3A
V3B
V4
1
4
7
2
5
8
3
6 1 3 6 9
2
5
1546
1549
8
1547
1550
1236
1545
CCD OUT
PBLK
OBCLP
CLPDM
ID/EXP
WEN/FLD
The number of SUB pulses is determined by the serial interface data. This chart shows the case where SUB pulses are output in each horizontal period. ID/EXP of this chart shows ID. ID is low for lines where CCD OUT contains the R component, and high for lines where CCD OUT contains the B component. In this drive mode, ID is reset to (high, low, high) in the horizontal periods of each readout block (A, B, C). WEN/FLD of this chart shows WEN. The shaded portion of OBCLP shows the range over which the wide OBCLP can be set by the serial interface data. VR of this chart is NTSC equivalent pattern 587H (1H: 2760ck) + 1500ck units. For PAL equivalent pattern, it is 704H + 960ck units.
1548
4
- 21 -
V5A
V5B
V6
CXD3615R
Chart-A2
Draft mode
* ICX432
Vertical Direction Timing Chart
MODE
Applicable CCD image sensor
VR
3 263 270 1 3
263
270 1
HR
SUB E E
V1
V2
V3A
V3B
V4
V5A
6
5
6
10
17
22
29
30
5
10
17
22 4 1 8 13 20
29 25
4
CCD OUT
1 8 13 20 25 28 1549
1532 1534
1537 1541 1544 1546
1549
1525 1527
1532 1534
1537 1541
PBLK
OBCLP
CLPDM
ID/EXP
WEN/FLD
The number of SUB pulses is determined by the serial interface data. This chart shows the case where SUB pulses are output in each horizontal period. ID/EXP of this chart shows ID. ID is low for lines where CCD OUT contains the R component, and high for lines where CCD OUT contains the B component. In this drive mode, ID is reset to low in the horizontal periods of each readout block (E). WEN/FLD of this chart shows WEN. The shaded portion of OBCLP shows the range over which the wide OBCLP can be set by the serial interface data. VR of this chart is NTSC equivalent pattern 269H (1H: 3004ck) + 2734ck units. For PAL equivalent pattern, it is 323H + 1708ck units.
1544 1546
28
30
- 22 -
V5B
V6
CXD3615R
Chart-A3
AF mode
* ICX432
Vertical Direction Timing Chart
MODE
Applicable CCD image sensor
VR
135 1 3 27 123 135 1 3 27
123
HR
SUB E
Frame shift block High-speed sweep block Frame shift block
G
High-speed sweep block
F
G
E
F
V1
V2
V3A
V3B
V4
V5A
6
4
481 485
488 490
PBLK
OBCLP
CLPDM
ID/EXP
WEN/FLD
1525 1527
4
CCD OUT
6
- 23 -
V5B
V6
CXD3615R
The number of SUB pulses is determined by the serial interface data. This chart shows the case where SUB pulses are output in each horizontal period. ID/EXP of this chart shows ID. ID is low for lines where CCD OUT contains the R component, and high for lines where CCD OUT contains the B component. In this drive mode, ID is reset to high in the horizontal periods of each readout block (E). WEN/FLD of this chart shows WEN. The shaded portion of OBCLP shows the range over which the wide OBCLP can be set by the serial interface data. VR of this chart is NTSC equivalent pattern 134H (1H: 3004ck) + 2869ck units. For PAL equivalent pattern, it is 161H + 2356ck units. In addition, for PAL equivalent pattern, the high-speed sweep block starts from 150H.
Chart-A4
Frame mode
200 300 400 500 600 700 800 900 1000
Horizontal Direction Timing Chart
* ICX432
MODE
Applicable CCD image sensor
(2760) 0
100
HR
MCKO
672 676 680
5
52
644
H1
H2
182 308
V1
266 392
V2
350 476
V3A/B
434 560
V4
518
140
V5A/B
224 602
- 24 -
670 674 646 670
V6
52
135
SUB
52
PBLK
20
44
OBCLP
50
OBCLP (wide)
CLPDM
140
ID/EXP
140
WEN/FLD
HR of this chart indicates the actual CXD3615R load timing. The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HR. The HR fall period should be between approximately 2.2 to 26.5s (when the drive frequency is 24.3MHz). This chart shows a period of 104ck (4.3s). SUB is output at the timing shown above when output is controlled by the serial interface data. ID and WEN are output at the timing shown above at the position shown in Chart-A1. OBCLP also has patterns of 14-38, 26-50 and 14-50 for a total of four patterns. OBCLP (wide) is output in the shaded portions shown in Chart-A1.
CXD3615R
These timings can be switched by the serial interface data.
Chart-A5
Draft/AF mode
200 300 400 500 600 700 800 900 1000
Horizontal Direction Timing Chart
* ICX432
MODE
Applicable CCD image sensor
(3004) 0
100
HR
MCKO
916 920 924
5
52
888
H1
H2
171 264 543 636
V1
233 326 605 698
V2
295 388 667 760
V3A/B
357 450 729 822
V4
419 512 791
140
V5A/B
202 481 574 853
- 25 -
V6
52
135
SUB
914
52
PBLK
20
44
OBCLP
918
50
OBCLP (wide)
890 914
CLPDM
140
ID/EXP
140
WEN/FLD
CXD3615R
HR of this chart indicates the actual CXD3615R load timing. The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HR. The HR fall period should be between approximately 2.2 to 26.5s (when the drive frequency is 24.3MHz). This chart shows a period of 104ck (4.3s). SUB is output at the timing shown above when output is controlled by the serial interface data. ID and WEN are output at the timing shown above at the position shown in Chart-A2 and A3. OBCLP also has patterns of 14-38, 26-50 and 14-50 for a total of four patterns. OBCLP (wide) is output in the shaded portions shown in Chart-A2 and A3. These timings can be switched by the serial interface data.
Chart-A6
Applicable CCD image sensor * ICX432
MODE Frame mode
Horizontal Direction Timing Chart (High-speed sweep: D)
(2760) 0 200 300 400 100 200
100
(2760) 0
HR
MCKO
5 52
5
52
H1
H2
176 248 284 356 392 1952 1988 2060 182
140
V1
158 194 266 302 374 410 1970 2006
V2
176 212 284 320 392 428 1988 2024
V3A/B
194 230 302 338 410 446 2006 2042
V4
212 248 320 356 428 1952 2024 140
140
- 26 -
158 230 266 338 374 446 1970 2042
V5A/B
224
V6 #1 #2 #3 #1039 #1040
52 135
52
135
SUB
PBLK
OBCLP
CLPDM
ID/EXP
WEN/FLD
HR of this chart indicates the actual CXD3615R load timing. The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HR. The HR fall period should be between approximately 2.2 to 26.5s (when the drive frequency is 24.3MHz). This chart shows a period of 104ck (4.3s).
CXD3615R
Chart-A7
Applicable CCD image sensor * ICX432
MODE AF mode
Horizontal Direction Timing Chart (Frame shift: F)
(3004) 0 200 300 400 500 600 700 800 900 1000
100
HR
MCKO
916 920 924
5
52
888
H1
H2
171 264 543 636 915 1008
V1
233 326 605 698 977
V2
295 388 667 760 1039
V3A/B
357 450 729 822
V4
419 512 791 884
140
- 27 -
202 481 574
V5A/B
853 946
V6 #1 #2
52
135
SUB
PBLK
OBCLP
CLPDM
ID/EXP
WEN/FLD
CXD3615R
HR of this chart indicates the actual CXD3615R load timing. The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HR. The HR fall period should be between approximately 2.2 to 26.5s (when the drive frequency is 24.3MHz). This chart shows a period of 104ck (4.3s). SUB is output at the timing shown above when output is controlled by the serial interface data. Frame shift of V1, V2, V3A/B, V4, V5A/B and V6 is performed up to 24H 1096ck (#78).
Chart-A8
Applicable CCD image sensor * ICX432
MODE AF mode
Horizontal Direction Timing Chart (High-speed sweep: G)
(3004) 0 200 300 400 500 600 700 800 900 1000
100
HR
MCKO
916 920 924
5
52
888
H1
H2
188 296 332 440 476 584 620 728 764 872 908 1016 1052
152
V1
176 212 320 356 464 500 608 644 752 788 896 932 1040
V2
200 236 344 380 488 524 632 668 776 812 920 956
V3A/B
224 260 368 404 512 548 656 692 800 836 944 980
V4
248 284 392 428 536 572 680 716 824 860 968 1004
140
- 28 -
164 272 308 416 452 560 596 704
V5A/B
740 848 884 992 1028
V6 #1 #2 #3
52
135
SUB
PBLK
OBCLP
CLPDM
ID/EXP
140
WEN/FLD
CXD3615R
HR of this chart indicates the actual CXD3615R load timing. The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HR. The HR fall period should be between approximately 2.2 to 26.5s (when the drive frequency is 24.3MHz). This chart shows a period of 104ck (4.3s). SUB is output at the timing shown above when output is controlled by the serial interface data. High-speed sweep of V1, V2, V3A/B, V4, V5A/B and V6 is performed up to 133H 2932ck (#114).
Chart-A9a
Frame mode
1254 1296 1338 1380 1420 1460 1502 1546
(2760) 0
Horizontal Direction Timing Chart
* ICX432
MODE
Applicable CCD image sensor
140
182
224
266
308
350
392
434
476
518
560
HR [A]
A Field
V1
V2
V3A/B
V4
V5A/B
- 29 -
[B]
V6
B Field
V1
V2
V3A/B
V4
V5A/B
V6
CXD3615R
HR of this chart indicates the actual CXD3615R load timing. The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HR. The HR fall period should be between approximately 2.2 to 26.5s (when the drive frequency is 24.3MHz). This chart shows a period of 104ck (4.3s).
602
(2760) 0
Chart-A9b
Frame mode
1086 1128 1170 1212 1254 1296 1338 1380 1420 1460
(2760) 0
Horizontal Direction Timing Chart
* ICX432
MODE
Applicable CCD image sensor
140
182
224
266
308
350
392
434
476
518
560
HR [C]
C Field
V1
V2
V3A/B
V4
V5A/B
V6
HR of this chart indicates the actual CXD3615R load timing. The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HR. The HR fall period should be between approximately 2.2 to 26.5s (when the drive frequency is 24.3MHz). This chart shows a period of 104ck (4.3s).
602
(2760) 0
- 30 -
CXD3615R
Chart-A10
Draft/AF mode
* ICX432
Horizontal Direction Timing Chart
MODE
Applicable CCD image sensor
1407
1438
1469
1500
1540
1580
1611
1642
1673
1704
1744
1784
1815
1846
1877
1908
140
171
202
233
264
295
326
357
388
419
450
481
512
543
574
605
636
667
698
HR
[E]
V1
V2
V3A
V3A
- 31 -
V4
V5A
V5B
V6
HR of this chart indicates the actual CXD3615R load timing. The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HR. The HR fall period should be between approximately 2.2 to 26.5s (when the drive frequency is 24.3MHz). This chart shows a period of 104ck (4.3s).
729
(3004) 0
(3004) 0
CXD3615R
Chart-A11
Draft Frame Draft
* ICX432
Vertical Direction Sequence Chart
MODE
Applicable CCD image sensor
VR
V1
V2
V3A
V3B
V4
V5A
- 32 -
C Close B 00 1 050h 000h 0 10 C (1st) C (2nd) 10 0 000h
V5B
V6 D
SUB
A
B
Mechanical shutter
Open C (3rd) 10 0 000h 00 1 050h D 00 1 050h
CCD OUT
A
MODE
00
00
SMD
1
1
SHR
050h
050h
This chart is a drive timing chart example of electronic shutter normal operation. Data exposed at B includes the blooming component. For details, see the CCD image sensor data sheet. The CXD3615R does not generate the pulse to control mechanical shutter operation. The switching timing of drive mode and electronic shutter data is not the same.
CXD3615R
Chart-B1
Frame mode
* ICX434
Vertical Direction Timing Chart
MODE
Applicable CCD image sensor
A Field
B Field
VR
25 31 650 1 24 31
650 1
HR
SUB A C
High-speed sweep block
C
High-speed sweep block
B
V1A
V1B
V2
V3A
1
3
5
2
7
9
4
6
8
1
3
5
7
9
10
2
4
6
11
13
15
17
19
21
23
25
27
8
10
1225
1227
1229
1231
1233
1228
1230
1232
1234
PBLK
OBCLP
CLPDM
ID/EXP
WEN/FLD
1236
1235
CCD OUT
12
- 33 -
V3B
V4
CXD3615R
The number of SUB pulses is determined by the serial interface data. This chart shows the case where SUB pulses are output in each horizontal period. ID/EXP of this chart shows ID. ID is low for lines where CCD OUT contains the R component, and high for lines where CCD OUT contains the B component. In this drive mode, ID is reset to (low, high) in the horizontal periods of each readout portion (A, B). WEN/FLD of this chart shows WEN. VR of this chart is NTSC equivalent pattern 650H (1H: 1848ck) units. For PAL equivalent pattern, it is 779H + 408ck units. This chart shows the pin configuration for the ICX434. (See page 4.)
Chart-B2
Draft mode
* ICX434
Vertical Direction Timing Chart
MODE
Applicable CCD image sensor
VR
12 16 325 1 12 16
325 1
HR
SUB D D
V1A
V1B
V2
V3A
4
9
4
2
7
9
2
10
15
18
23
26
31
34
39
42
47
50
55
58
63
7
10
15
18
23
26
31
1207
1210
1215
1218
1223
1226
1231
1234
1202
1207
1210
1215
1218
1223
1226
1231
PBLK
OBCLP
CLPDM
ID/EXP
WEN/FLD
The number of SUB pulses is determined by the serial interface data. This chart shows the case where SUB pulses are output in each horizontal period. ID/EXP of this chart shows ID. ID is low for lines where CCD OUT contains the R component, and high for lines where CCD OUT contains the B component. In this drive mode, ID is reset to high in the horizontal period of the readout portion. WEN/FLD of this chart shows WEN. VR of this chart is NTSC equivalent pattern 325H (1H: 1848ck) units. For PAL equivalent pattern, it is 389H + 1128ck units. This chart shows the pin configuration for the ICX434. (See page 4.)
1234
CCD OUT
34
- 34 -
V3B
V4
CXD3615R
Chart-B3
Frame mode
50 100 150 200 250
Horizontal Direction Timing Chart
* ICX434
MODE
Applicable CCD image sensor
(1848) 0
HR
MCKO
56 188
H1
H2
72 120
V1A/B
104 152
V2
56 136
V3A/B
88 168
V4
88 152
- 35 -
56 45 51 104 104
SUB
214
PBLK
19
OBCLP
216
OBCLP (wide)
190 214
CLPDM
ID/EXP
WEN/FLD
HR of this chart indicates the actual CXD3615R load timing. The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HR. The HR fall period should be between approximately 3.1 to 10.4s (when the drive frequency is 18MHz). This chart shows a period of 104ck (5.8s). SUB is output at the timing shown above when output is controlled by the serial interface data. ID and WEN are output at the timing shown above at the position shown in Chart-B1. OBCLP also has patterns of 13-39, 25-51 and 13-51 for a total of four patterns. OBCLP (wide) is output in the shaded portions shown in Chart-B1.
CXD3615R
These timings can be switched by the serial interface data. This chart shows the pin configuration for the ICX434. (See page 4.)
Chart-B4
Draft mode
50 100 150 200 250
Horizontal Direction Timing Chart
* ICX434
MODE
Applicable CCD image sensor
(1848) 0
HR
MCKO
56 188
H1
H2
56 88 120 152
V1A/B
72 104 136 168
V2
56 88 120 152
V3A/B
72 104 136 168
V4
88 152
- 36 -
56 45 51 104 104
SUB
214
PBLK
19
OBCLP
216
OBCLP (wide)
190 214
CLPDM
ID/EXP
WEN/FLD
HR of this chart indicates the actual CXD3615R load timing. The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HR. The HR fall period should be between approximately 3.1 to 10.4s (when the drive frequency is 18MHz). This chart shows a period of 104ck (5.8s). SUB is output at the timing shown above when output is controlled by the serial interface data. ID and WEN are output at the timing shown above at the position shown in Chart-B2. OBCLP also has patterns of 13-39, 25-51 and 13-51 for a total of four patterns. OBCLP (wide) is output in the shaded portions shown in Chart-B2.
CXD3615R
These timings can be switched by the serial interface data. This chart shows the pin configuration for the ICX434. (See page 4.)
Chart-B5
Applicable CCD image sensor * ICX434
MODE Frame mode
100 150 200 250
Horizontal Direction Timing Chart (High-speed sweep: C)
50
(1848) 0
HR
MCKO
56 188
H1
H2
56 84 112 140 168 196 224 252
V1A/B
70 98 126 154 182 210 238 266
V2
56 84 112 140 168 196 224 252
V3A/B
70 98 126 154 182 210 238 266
V4 #1
88 152
- 37 -
#2
#3
#4
SUB
PBLK
OBCLP
CLPDM
ID/EXP
WEN/FLD
HR of this chart indicates the actual CXD3615R load timing. The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HR. The HR fall period should be between approximately 3.1 to 10.4s (when the drive frequency is 18MHz). This chart shows a period of 104ck (5.8s). SUB is output at the timing shown above when output is controlled by the serial interface data. ID and WEN are output at the timing shown above at the position shown in Chart-B1. High-speed sweep of V1A/B, V2, V3A/B and V4 is performed up to 22H 1848ck (#758). This chart shows the pin configuration for the ICX434. (See page 4.)
CXD3615R
Chart-B6
Frame mode
1027 1029 1071 1091 1131 1133 1175
Horizontal Direction Timing Chart
* ICX434
(1848) 0 56 72 88 104 120 136 152 168
MODE
Applicable CCD image sensor
(1848) 0
56 72 88 104 120 136 152 168 184 200 216
HR [A]
A Field
V1A
V1B
V2
V3A
V3B
V4 [B]
- 38 -
Logical alignment
B Field
V1A
V1B
V2
V3A
V3B
V4
HR of this chart indicates the actual CXD3615R load timing. The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HR. The HR fall period should be between approximately 3.0 to 13.4s (when the drive frequency is 18MHz). This chart shows a period of 104ck (5.8s). This chart shows the pin configuration for the ICX434. (See page 4.)
CXD3615R
Chart-B7
Draft mode
* ICX434
Horizontal Direction Timing Chart
MODE
Applicable CCD image sensor
1027 1029
1071
1091
1111
1131 1133
56 72 88 104 120 136 152 168
1175
(1848) 0 56 72 88 104 120 136 152 168
(1848) 0
HR [D]
V1A
V1B
V2
V3A
V3B
- 39 -
V4
HR of this chart indicates the actual CXD3615R load timing. The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HR. The HR fall period should be between approximately 3.1 to 10.4s (when the drive frequency is 18MHz). This chart shows a period of 104ck (5.8s). This chart shows the pin configuration for the ICX434. (See page 4.)
CXD3615R
Chart-B8
Draft Frame Draft
* ICX434
Vertical Direction Sequence Chart
MODE
Applicable CCD image sensor
VR
V1A
V1B
V2
V3A
- 40 -
C D E B Close 00 00 1 050h 050h 1 00 1 050h 10 0 050h C D E
V3B
V4 F
SUB
A
B
CCD OUT
A
E Open 10 0 050h 00 1 050h
F
Mechanical shutter
MODE
00
00
00 1 050h
SMD
1
1
SHR
050h
050h
CXD3615R
This chart is a driving timing chart example of electronic shutter normal operation. Data exposed at D includes the blooming component. For details, see the CCD image sensor data sheet. The CXD3615R does not generate the pulse to control mechanical shutter operation. The switching timing of drive mode and electronic shutter data is not the same. This chart shows the pin configuration for the ICX434. (See page 4.)
Chart-Z
* ICX432/ICX434
High-Speed Phase Timing Chart
MODE
Applicable CCD image sensor
HR
HR'
CKI
CKO
ADCLK 56/52 188/644/888
1
MCKO
H1
- 41 -
H2
RG
XSHP
XSHD
HR' indicates the HR which is the actual CXD3615R load timing. The phase relationship of each pulse shows the logical position relationship. For the actual output waveform, a delay is added to each pulse. The logical phase of ADCLK can be specified by the serial interface data.
CXD3615R
CXD3615R
Application Circuit Block Diagram
CCD ICX432 ICX434
CCD OUT S/H A/D
D0 to D9 10
CLPDM
OBCLP
H1 H2 RG V4 V2 V5A V5B V1 V3A V3B V6 SUB
16 17 19 20 22 12 13 9 38 39 40 42 43 44 46 47 48 26 18 21 V-Dr TG CXD3615R
ADCLK
23 25 30 34 SSG 35 CKO MCKO VR HR Signal Processor Block
XSHD
XSHP
PBLK
4 5 2 3 6 31 32 33
ID/EXP WEN/FLD
RST SNCSL SSGSL
TEST1
TEST2
CKI
SSI
V1 and V2 only for ICX432
SCK
SEN
Controller
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
Notes for Power-on Of the three -7.5V, +15.0V, +3.3V power supplies, be sure to start up the -7.5V and +15.0V power supplies in the following order to prevent the SUB pin of the CCD image sensor from going to negative potential.
15.0V
t1
20% 0V 20%
t2 t2 t1 -7.5V
- 42 -
CXD3615R
Package Outline
Unit: mm
48PIN LQFP (PLASTIC)
9.0 0.2 36 37 7.0 0.1 25 24 S
(8.0)
A 48 1 0.5 + 0.08 0.18 - 0.03 + 0.2 1.5 - 0.1 12 13
B
(0.22)
+ 0.05 0.127 - 0.02 0.13 M
0.1 0.1 0.1
0.127 0.04
0.5 0.2
S
0.18 0.03
0.5 0.2
0 to 10
DETAIL B: PALLADIUM DETAIL A NOTE: Dimension "" does not include mold protrusion.
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE LQFP-48P-L01 P-LQFP48-7x7-0.5 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN PALLADIUM PLATING COPPER ALLOY 0.2g
- 43 -
Sony Corporation

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